BiCMOS circuit optimisation technique linking channelwidth of MOS device to collector design of BJT

Journal article

Peer reviewed

S.S. Rofail, Y.K. Seng and Kiat Seng Yeo

Electronics letters, Vol.32(25), pp.2300-2301

05/12/1996

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Title: BiCMOS circuit optimisation technique linking channelwidth of MOS device to collector design of BJT
Creators - without role: S.S. Rofail - Nanyang Technological University
Y.K. Seng - Nanyang Technological University
Kiat Seng Yeo - Office of Provost
Publication Details: Electronics letters, Vol.32(25), pp.2300-2301
Identifiers: 9912505309846
Academic Unit: Office of Provost
Language: English
Resource Type: Journal article