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Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel
Journal article   Peer reviewed

Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel

Eu Jin Tan, Kin-Leong Pey, Navab Singh, Guo-Qiang Lo, Dong Zhi Chi, Yoke King Chin, Keat Mun Hoe, Guangda Cui and Pooi See Lee
IEEE electron device letters, Vol.29(10), pp.1167-1170
01/10/2008

Abstract

Engineering Engineering, Electrical & Electronic Science & Technology Technology
We have fabricated silicon nanowire N-MOSFETs using erbium disilicide (ErSi2-x) in a Schottky source/drain back-gated architecture. Although the subthreshold swing (similar to 180 mV/dec) and drain-induced barrier lowering (similar to 500 mV/V) are high due thick BOX as gate oxide, the fabricated Schottky transistors show acceptable drive current similar to 900 mu A/mu m and high I-on/I-off ratio (similar to 10(5)). This is attributed to the improved carrier injection as a result of low Schottky barrier height (Phi(b)) of ErSi2-x/n - Si(similar to 0.3 eV) and the nanometer-sized (similar to 8 nm) Schottky junction. The carrier transport is found to be dominated by the metal-semiconductor interface instead of the channel body speculated from the channel length independent behavior of the devices. Furthermore, the transistors exhibit ambipolar characteristics, which are modeled using thermionic/thermionic-field emission for positive and thermionic-tield emission for negative gate biases.

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