Abstract
In this study, we propose a novel stackable Si1−xGex nanosheet gate-controlled thyristor (GCT) 1T0C DRAM design, utilizing thyristor-based positive feedback. This design eliminates the need for a separate capacitor, addressing key scalability and power challenges in conventional 1T1C DRAM. Through Technology Computer-Aided Design (TCAD) simulations, we demonstrate that the Si0.9Ge0.1 nanosheets GCT DRAM achieves an on-state current of 2.3 × 10−4 A, with a voltage hysteresis of over 1.8 V. Furthermore, an extensive material and geometric optimization analysis was conducted, revealing that the GCT device channels can be effectively scaled down to 10 nm. The Si0.8Ge0.2 nanosheet GCT DRAM exhibits a hysteresis memory window exceeding 1.5 V, an exceptionally high on/off current ratio of 109, and a sensing current window of 216 μA. Additionally, the Si0.57Ge0.43 nanosheet GCT DRAM can reduce the positive feedback voltage (Vfb) to below 0.8 V. This advancement significantly reduces the operating power consumption of the device, making it suitable for next-generation, energy-efficient DRAM applications.