Abstract
This letter presents a D-band CMOS wideband power amplifier (PA). The neutralizing capacitor and magnetically coupled resonator (MCR) matching network are designed and implemented to expand the operating bandwidth. In addition, the synchronous gate signal feeding (SGSF) transistor and the multistage staggering (MS) scheme-based high-coupling coefficient (K-m) transformer are analyzed and utilized for structuring all the amplification cells to further expand the 1-dB operation bandwidth. Fabricated in 40-nm CMOS process, the PA chip operates at 160 GHz with 31-GHz (19.8%) 1-dB bandwidth and a peak S-21 of 15.5 dB. The maximum saturated output power (P-SAT) and the peak power-added efficiency (PAE) are 10.3 dBm and 9.4%, respectively. The circuit occupies 0.022-mm(2) core area only, obtaining a high power density of 487 mW/mm(2).