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Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment
Journal article   Peer reviewed

Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment

SHL Seah, Kiat Seng Yeo, Jian Guo Fia, Manh Anh Do and Kiat Seng Yeo
IEEE transactions on electron devices, Vol.48(5), pp.1001-1004
01/05/2001
DOI: https://doi.org/10.1109/16.918250

Abstract

Channels Devices Drains Electric potential Extraction Mathematical models Routines Voltage
The effective channel length L sub(eff) and total external series resistance R sub(TOText) of deep submicron lightly doped drain (LDD) pMOSFETs, operating in a Bi-MOS hybrid-mode environment, have been modeled as functions of bias and temperature. The accuracy of the device threshold voltage used in the L sub(eff) and R sub(TOText) extraction routine is discussed. The proposed models have been verified for temperature ranging from 223 K to 398 K and source-to-body voltage V sub(SB)>0 V conditions

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