Abstract
In this work, we demonstrate a two-step analysis procedure that enables an in-depth understanding of the localized charge trapping and charge decay mechanisms in metal nanocrystal (MNC)-embedded high-kappa/SiO2 gate stacks. The results clearly reveal that vertical charge loss and lateral charge diffusion are two competing mechanisms, and they can be identified by discharging current measurements at elevated temperatures and the Kelvin force microscopy characterization. It is found that the MNC with higher work function has a lower inter-dot charge tunneling probability, which is favorable for improved retention in memory applications. However, the vertical charge loss during the initial decay period is a trade-off and it could be minimized by using a dual-layer MNC structure. (C) 2011 American Institute of Physics. [doi:10.1063/1.3664220]