Abstract
In a bus with n wires, each wire has two states, '0' or '1', representing one bit of information. Whenever the state transitions from '0' to '1', or '1' to '0', joule heating causes the temperature to rise, and high temperatures have adverse effects on on-chip bus performance. Recently, the class of low-power cooling (LPC) codes was proposed to control such state transitions during each transmission. As suggested in earlier work, LPC codes may be used to control simultaneously both the peak temperature and the average power consumption of on-chip buses. Specifically, an (n,t,w) -LPC code is a coding scheme over n wires that (i) avoids state transitions on the t hottest wires (thus preventing the peak temperature from rising); and (ii) allows at most w state transitions in each transmission (thus reducing average power consumption). In this paper, for any fixed value of w , several constructions are presented for large LPC codes that can be encoded and decoded in time O\left ({n \log ^{2} (n/w)}\right) along with the corresponding encoding/decoding schemes. In particular, we construct LPC codes of size (n/w)^{w-1} , which are asymptotically optimal. We then modify these LPC codes to also correct errors in time O(n^{3}) . For the case where w is proportional to n , we further present a different construction of large LPC codes, based on a mapping from cooling codes to LPC codes. Using this construction, we obtain two families of LPC codes whose encoding and decoding complexities are O(n^{3}) .