Logo image
Physical analysis of breakdown in high-kappa/metal gate stacks using TEM/EELS and STM for reliability enhancement (invited)
Journal article   Peer reviewed

Physical analysis of breakdown in high-kappa/metal gate stacks using TEM/EELS and STM for reliability enhancement (invited)

Kin Leong Pey, Nagarajan Raghavan, Xing Wu, Wenhu Liu, Xiang Li, Michel Bosman, Kalya Shubhakar, Zin Zar Lwin, Yining Chen, Hailang Qin, …
Microelectronic engineering, Vol.88(7), pp.1365-1372
01/07/2011

Abstract

Engineering Engineering, Electrical & Electronic Nanoscience & Nanotechnology Optics Physical Sciences Physics Physics, Applied Science & Technology Science & Technology - Other Topics Technology
In this invited paper, we demonstrate how physical analysis techniques that are commonly used in integrated circuits failure analysis can be applied to detect the failure defects associated with ultrathin gate dielectric wear-out and breakdown in high-kappa materials and investigate the associated failure mechanism(s) based on the defect chemistry. The key contributions of this work are perhaps focused on two areas: (1) how to correlate the failure mechanisms in high-kappa/metal gate technology during wear-out and breakdown to device processing and materials and (2) how the understanding of these new failure mechanisms can be used in proposing "design for reliability" (DFR) initiatives for complex and expensive future CMOS nanoelectronic technology nodes of 22 nm and 15 nm. Hf-based high-kappa materials in conjunction with various gate electrode technologies will be used as main examples while other potential high-kappa gate materials such as cerium oxide (CeO2) will also be demonstrated to further illustrate the concept of DFR. (C) 2011 Elsevier B.V. All rights reserved.

Metrics

1 Record Views

Details

Logo image