Abstract
A comprehensive modeling approach combining Kinetic Monte Carlo method and the Finite Element Method is presented in this study for simulating the degradation behavior of split gate non-volatile memory. The oxide layer between erase gate and floating gate is proved to be the weakest link, caused by the intensive electrical field enhancement during the erase process. The clustering effect shown by the simulated reading current distribution indicates the impact of process induced traps and corresponding early failures. Moreover, the simulation results of endurance test also show a good resemblance of the trends from experimental data. Based on both simulation and experimental data, the prediction of endurance limit regarding read reference level is provided. Our statistical modeling approach can be applied as a design for reliability tool, offering a comprehensive assessment of the reliability requirements for wide range of operating conditions and different layout schemes.