Abstract
A comprehensive study is presented of the effects of temperature and well-implant energy on the performance and short channel characteristics of 0.25 mu m pMOSFETs. Tradeoffs between performance and short-channel effects (SCEs) are examined experimentally based on the device on-current (I sub(on)), off-current (I sub(off)), saturation transconductance (Gm), drain-induced barrier lowering (DIBL), and punch-through effect ratio ( Delta S/S%).