Abstract
An improved zero-bias thermally stimulated current (TSC) technique was successfully applied to characterize the traps in semi-insulating gallium arsenide buffer layers grown at low temperature by molecular beam epitaxy (MBE) for the reduction of backgating in gallium arsenide based integrated circuits. Conventional TSC technique is not suitable because of the strong leakage current in those buffer layers. Special precaution is needed to suppress the leakage current even when the bias is nominally zero. An electron trap with an activation energy of 0.52 eV was found in annealed buffer layers. In addition, a continuum of states, which were attributed to the interface states at the interface of arsenic precipitates and bulk gallium arsenide, was also detected.