Abstract
Dopant segregated Schottky barrier (DSSB) and Schottky barrier (SB) vertical silicon nanowire (VSiNW) diodes were fabricated using industry complemetary metal oxide semiconductor field effect transistor (CMOS) processes to investigate the effects of segregated dopants at the silicide/silicon interface and different annealing steps on nickel silicide formation in the DSSB VSiNW diodes. With segregated dopants at the silicide/silicon interface, VSiNW diodes showed higher on-current, due to an enhanced carrier tunneling, and much lower off-current. This can be attributed to the altered energy bands caused by the accumulated Arsenic dopants at the interface. Moreover, DSSB VSiNW diodes also presented ideality factor much closer to unity and exhibited lower electron Schottky barrier height (Phi(Bn)) than SB VSiNW diodes. This proved that interfacial accumulated dopants could impede the inhomogeneous nature of the Schottky diodes and simultaneously, minimize the effect of Fermi level pinning and ionization of surface defect states. Comparing the impact of different silicide formation annealing sequence using DSSB VSiNW diodes, the 2-step anneal process reduces the silicide intrusion length within the SiNW by similar to 5x and the silicide interface was smooth along the (100) direction. Furthermore, the 2-step DSSB VSiNW diode also exhibited much lower leakage current and an ideality factor much closer to unity, as compared to the 1-step DSSB VSiNW diode. (C) 2012 The Japan Society of Applied Physics